The present invention generally relates to computer architectures and particularly to a dedicated context-cycling microprocessor which is capable of functioning as either a stand-alone processor or as an intelligent interface between one or more external devices and the shared data memory of another computer, such as a Harvard architecture computer.
To achieve high speed, some multiprocessor computers employ specialized dedicated processors for handling specific tasks. For example, it is common to supplement the main central processing unit with a separate math coprocessor, the math coprocessor being specifically designed to perform arithmetic computations at high speed. Although the math coprocessor may perform different computational functions (add, subtract, multiply, divide) these functions are all of the same type or class. A math coprocessor would not be suitable to handle asynchronous data communication in addition to its other arithmetic functions. The math coprocessor is an example of a special purpose processor for a multiprocessor architecture that is dedicated to performing only one task.
As multiprocessor computer systems become more sophisticated, single purpose coprocessors begin to have drawbacks. It would be desirable if multiprocessor systems could be designed to support different classes of tasks by the coprocessor. For example, The Dow Chemical Company has developed a common core computer that employs a Harvard architecture computer as its main central processing unit. The Applicants' assignee has found the Harvard architecture to be highly desirable in process control applications where high speed performance is of utmost importance. The context-cycling microprocessor of the present invention works as an asynchronous data communication handler for this Harvard architecture common core computer.
A computer which includes the following characteristics is generally referred to as having a "Harvard" architecture. Namely, the computer will be designed with separate instruction and data stores and independent buses will be provided to enable the central processing unit (CPU) of the computer to communicate separately with each of these stores. Contrast this architecture with the "von Neumann" or "Princeton" based computer architecture, which generally employs the same physical store for both instructions and data, and a single bus structure for communication with the CPU.
Various approaches have been taken to designing a microcomputer or microprocessor with a Harvard architecture, as represented by the following patents: Yasui et al., U.S. Pat. No. 5,034,887, issued on Jul. 23, 1991, entitled "Microprocessor With Harvard Architecture"; Portanova et al., U.S. Pat. No. 4,992,934, issued on Feb. 12, 1991, entitled "Reduced Instruction Set Computing Apparatus And Methods"; Mehrgardt et al., U.S. Pat. No. 4,964,046, issued on Oct. 16, 1990, entitled "Harvard Architecture Microprocessor With Arithmetic Operations And Control Tasks for Data Transfer Handled Simultaneously"; and Simpson, U.S. Pat. No. 4,494,187, issued on Jan. 15, 1985, entitled "Microcomputer With High Speed Program Memory." Additionally, it should be noted that the Intel i860 64-bit microcomputer has been described as having an on-board Harvard architecture due to the provision of separate instruction and data cache paths. In this regard, a description of the Intel i860 chip design may be found in i860 Microprocessor Architecture, by Neal Margulis, Osborne McGraw-Hill 1990.
The use of separate instruction and data communication paths in a Harvard architecture machine effectively increases the overall speed of the computer by enabling an instruction to be accessed at the same time that data for this or another instruction is accessed. In the context of programmed operations, the instruction is usually referred to as the "opcode" (the operation code), and the data is referred to the "operand." While the benefit in speed of using the Harvard architecture is significant, a significant advance in this design has also been described in commonly assigned Sederlund et al., U.S. patent application Ser. No. 08/319,453, filed on Oct. 6, 1994, entitled "An Extended Harvard Architecture Memory System." This extended memory system employs an address store for containing an ordered sequence of program memory addresses. The address store (referred to as "queue memory") determines the sequence of operations to be implemented through its list of program memory addresses. In this regard each of these program memory addresses identifies the location of the first instruction of a particular subroutine which is contained in the program memory. The address store may also contain the addresses of one or more subroutine arguments which are, in turn, contained in either a value store or in a data memory. Thus, the address store may be utilized as a location server for both the program memory and the data memory of a computer which is based upon the Harvard architecture.
As the preceding suggests, The Dow Chemical Company is committed to the use of highly advanced computer systems that are uniquely suited to process control applications. In this regard, whereas the massively multiplexed CPU design, based on a Harvard architecture, is highly efficient at performing process control instructions at very high speed, another computer architecture is needed to best handle numerous asynchronous events that occur in process control applications. In this regard, although The Dow Chemical Company envisions its massively multiplexed CPU design and the dedicated context-cycling computer of the present invention to be well suited to chemical and manufacturing process applications, the foregoing innovations are equally suited to all other types of process control applications, ranging from power plant to spacecraft.
The present invention provides a dedicated context-cycling microprocessor or computer for handling the input and output tasks on behalf of its associated Harvard architecture central processing unit. As it turns out, providing this functionality is not as easy as it might appear. In a complex process control system there are many widely varying input/output functions and asynchronous events that must be handled. Inasmuch as the main process control computer has been designed to operate at extremely high speeds, the input/output functions must also be handled at comparable high speeds, otherwise the input/output becomes a bottleneck in the system. One approach, consistent with conventional practice, would be to provide a separate coprocessor for each input/output function. However, this would dramatically increase the cost of the system and would unduly complicate the interface between the main processor and the input/output processors.
Another approach would be to employ a single coprocessor that may be programmatically cycled through different functional states. However, such an approach has not heretofore been feasible because of the computational overhead required to save one context state before operating the next.
The present invention solves the problem by providing a dedicated context-cycling microprocessor that has dedicated registers and program counters for each different functional context. As used herein the term "context" (within a processor) refers to a specialized physical circuit having a dedicated program counter to identify the current location in a program instance for fetching an op code for execution in a computational unit--such as the computational unit of a general purpose computer processor. The specialized physical circuit is useful for exchanging data between external entities and the configuration and computational assets of the processor (including the computational unit) according to a predefined protocol, or for performing predefined data manipulation functions. The context may also include an embedded state machine that may operate independently of the computational unit to aid in the exchange of data.
In the preferred configuration, a plurality of contexts share common assets, such as by time division multiple access, each context cycling through active and inactive states according to a context priority scheme. Common assets are assets actively used by only one context at a time (such as, without limitation, external data memory, computational unit, comparator, program counter calculator and local memory). Each context assumes one of a plurality of functional states, including at least one active state and at least one inactive state. In the active state the context may communicate with the computational unit and may also use other common assets. In the inactive state, the embedded state machine of a context may continue to function although the program counter of its context is not being used to identify an op code for the manipulation of configuration and computational assets. Each context has a data store, such as a memory or register, for retaining the process and configuration state of pertinent resources, attributes, or aspects associated with either the interface or the function while another context is active. In the preferred embodiment, each context is configured as an embedded microcontroller associated with a processor for performing mathematical computatations.
The context-cycling microprocessor rapidly cycles from context to context without the usual overhead of saving state; the dedicated registers and program counters automatically save state without wasting processor cycles as in the conventional practice.
Accordingly, it is a principal objective of the present invention to provide a microprocessor design which has special capabilities for handling input/output and asynchronous events.
It is a more specific objective of the present invention to provide a microprocessor design which is capable of dynamically cycling between a number of both device and time handling contexts.
It is another objective of the present invention to provide a context-cycling microprocessor design which may be utilized in either a stand-alone processor or as an intelligent communication interface for another processor which operates as the source and destination of data.
It is a further objective of the present invention to provide a context-cycling microprocessor design which is capable of acting as a time-line enforcer.
It is an additional objective of the present invention to provide a context-cycling microprocessor design which is also capable of acting as a plurality of distinct, but coordinated controllers for processing communication requests with external devices.
It is also an objective of the present invention to provide a context-cycling microprocessor design which is capable of not only rapidly handling external communication requests, but also capable of managing a shared memory system in conjunction with another microprocessor.